A clock signal is a signal that oscillates between two states and is used to trigger actions of synchronous digital circuits, i.e. clocked circuits. A signal may be a time varying physical quantity carrying information, e.g. a varying voltage level. In an integrated circuit, for example, many circuit elements or devices, such as for example, flip-flop circuits or memory circuits, may operate synchronously with a clock signal. The clock signal may usually be generated by a clock source or clock generator circuit, for example a local oscillator circuit.
In order to serve as a common trigger and time reference for the connected synchronous circuits, the same clock signal is distributed to all connected circuits that require the clock signal. A clock signal distribution network, which may, for example, be organized as a clock tree with the connection to the clock source as root, branches, and leafs connected to the clocked circuits, may be used to distribute the clock signal from the clock source or a common point connected to the clock source to the clocked circuits.
Since the synchronized, clocked circuits and generated data signals refer to the clock signal as a temporal reference, the clock waveforms must be particularly sharp. Due to, for example, different lengths of nets, i.e. connecting lines or wirings, between the clock source and the clocked circuits, or differences between their physical characteristics, a difference between periods of time for the clock signal to reach each of the clocked circuits may occur, which may be referred to as clock skew. Too large clock skew may, for example, confuse timing between input and output of clocked circuits and may result in wrong behavior of the clocked circuits or of an integrated circuit containing the clocked circuits and the clock signal distribution network.
Since clock skew depends, for example, on the dimensions of the circuits and wirings, clock skew handling may be especially important for small semiconductor processes where large process variations on the integrated circuit die may occur.
A clock distribution network may contain clock signal driving circuits, for example clock buffers, inverters, e.g., two serially connected inverter circuits, or any other circuits capable of driving signals, for providing a received clock signal to connected wirings or nets with recovered waveform and improved timing. At the same time, the clock signal driving circuits are subject to variation caused by process imperfections.
In order to improve, for example, setup and hold timing of an integrated circuit design, it may contain clock skew handling circuitry. For example, in U.S. Pat. No. 6,696,863, a clock signal distribution circuit is shown that uses a mesh clock tree architecture for reducing the clock skew. A clock tree architecture is used for distributing a clock signal to the connected clocked circuits, wherein the last, i.e. the highest or topmost, level of the clock tree, that contains tree leafs connected to the clocked circuits has the leaf nets interconnected with each other in a mesh grid structure. In U.S. Pat. No. 7,392,495, a block structure of local balanced clock trees with blocks connected in a mesh grid structure is shown.